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As you may know, those little electronic chips that go into practically everything these days are called "chips" for the simple reason that they are pieces cut from large thin "wafers" of processed silicon. Depending on the size of the wafer and the quantity of desired circuitry, there could be several
hundred chips cut out of each wafer. There is something of a dilemma faced by chip manufacturers, caused by the fact that the manufacturing process is imperfect, and so there is always some significant percentage of defective chips. (That percentage varies with the manufacturer, and is usually kept secret, but 25% is not uncommon.)
Part of the dilemma is that the whole idea of "integration" is to put as many electronic-function circuits onto a chip as possible. But this leads to larger chips, which means fewer of them can fit on a wafer. Since the cost of wafers and wafer porcessing is mostly fixed, fewer larger chips means each must be priced higher than when many small chips can be cut from a wafer. Those defective chips lead to even higher prices. Worse, and the more subtle aspect of the dilemma, is that the occurance of defects is often random (frequently caused by dust particles). That 25% I mentioned might be true for one chip size, but wildly low for some other chip size. The way to think of it is in terms of "defects per wafer" and not defects per chip. If that number of defects can be held constant, then when there are a lot of chips cut from a wafer, the percentage of bad chips is low, while when few chips are cut from a wafer, the percentage of bad chips is high. It often takes only one defect to ruin a chip, see.
With the preceding as background information, consider that the natural trend for Large Scale Integration is to make larger and larger chips, until some day one can envision an entire wafer being used as a single "chip". Such "Wafer Scale Integration" has been attempted before, but the defect rate has so far made the notion far too impractical. Still, there are a couple variations of the idea which ARE practical, and which I wish to describe here.
First, consider the simple fact that the technology of chip making has improved vastly over the last three and a half decades. The two most important aspects have been "line width" and cleanliness. The latter obviously refers to control of dust particles, and the former refers to the thickness of the circuit wiring that is traced out on a chip. Originally 40 microns (millionths of a meter) wide in 1965, nowadays many circuit lines are drawn at 0.09 micron, or even less. They absolutely have to have extremely clean conditions to prevent dust from interfering with such fine precision. Well, the thing I wish to point out is that the Idea of Wafer Scale Integration has been around for quite a while, but somehow nobody seems to be considering the possibility of combining today's cleanliness with yesterday's line width.
In other words, today's cleanliness traps practically all dust particles larger than a micron, so what if it was decided to use a line width of 4 microns? Small-enough dust particles do not cause circuit failures! Sure, the circuitry on a such a wafer would run slower than today's top speeds, and the wafer would probably be somewhat power-hungry, but the point is that this kind of Wafer Scale Integration could be DONE -- reliably and workably -- and very probably would prove useful somewhere. Overall, see, due to packaging and mounting of individual component chips on an ordinary circuit board, a comparable Integrated Wafer even with such large line widths will still come out on top in terms of more compact total size.
The other variation of Wafer Scale Integration that I wish to describe also uses relatively wide line widths, but in this case the wafer contains relatively few actual circuits. This wafer is intended to be used in conjuction with specialized fine-line chips, in the following overall fashion:
Consider a Central Processing Unit, the CPU or "processor" at the heart of a modern personal computer. Inside this quite-large chip are regions devoted to various specialized tasks. For example, one region might be "Cache Memory",
another might be the "Arithmetic/Logic Unit", another might be the "Floating Point Unit", and so on. In this example, let's pretend there are half-a-dozen major components to such a processor.
Well, when such a chip is manufactured, it will probably be declared defective if any of its major components is defective. This is something of a shame, because the other five components may be perfectly fine -- but since they were all integrated together into a single chip, that's just the way the cookie crumbles. Well, suppose there was a way to make those components separately, and combine only good ones into an overall same-sized CPU? That is exactly what I'm going to attempt to describe here!
Consider that when a chip is designed, the surface of the chip is provided with a number of "contact points", where tiny wires will be attached to it, so it can communicate with the outside world. These contact points are generally quite a bit larger than the fine line-widths inside the chip, and this is to compensate for the difficulty in attaching those fine wires. Thus it is certainly quite possible to use smaller (and more numerous) contact points, provided that a way
existed to reliably connect them.
Simple -- and this is where the overall wafer comes in. This wafer is designed to accommodate those contact points, as in the following minimal sketch:
1 2 3 ___ 3 2 1
4 5 6 ___ 6 5 4
7 8 9 ___ 9 8 7
At left are nine contact points on a wafer, and at right are nine contact points on a chip. Just turn the chip upside-down, align, and thermally bond. This should work even for hundreds of connections at once. In this scenario, the wafer becomes a kind of circuit board, to hold many chips very close together, especially for the half-dozen individual-component chips in our example, that would work together to be a CPU. Note that since the purpose of the wafer is just to connect mounted chips, the curcuit-lines it contains can all be relatively wide, which in turn is a good guarantee of high wafer yields. And being able to construct those lines at different depths and directions within the wafer, using standard processing techniques, is just a plus!
Now I do realize that such a contructed CPU will not be able to operate QUITE as fast as a single truly integrated CPU having shorter-length internal connections, but the speed should still be quite good since the components ARE to be constructed using fine lines, and they WILL be located very close together -- but the supreme advantage to this kind of Wafer Scale Integration is cost. Those individual component chips can be cranked out with as low a defect-percentage as can be expected when making small chips, as previously described.
Obviously, with a whole wafer full of contact points to play with, it becomes easy to keep adding chips until the wafer is full, and the total conglomeration is practically a supercomputer in its own right, including memory chips, multiple processors, graphics chips, communications chips (SCSI, FireWire, ATA, RAID, etcetera), sound chips, and so on, and so on, and so on.
Finally, it must be mentioned that whole wafers are not hardly cheap, and so this Idea is not quite so economical at this time, and thus it has to wait until ways can be implemented to more efficiently make flat sheets of silicon. I think I've posted something about that, already :)
On making lots of flat silicon
http://www.halfbake...con_20Manufacturing
As mentioned above :) [Vernon, Oct 04 2004]
[link]
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the two major catches to this would be:
- It works out significantly cheaper (on a large scale) to accept a high failure rate on cheaper components than to pay a higher price for a smaller failure rate.
- When the frequency tops around 1GHz, the larger track width becomes a resistance as the tracks start to form more of a transmission line model than a short line model. This would mean also that the power would need to be ramped up and the resultant crosstalk would mean that the line seperation would also need to be increased at a similar rate to the line width. |
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reap, can I assume you are referring to the second of the two suggestions? The first one specifically states that it would not be suitable for high speeds such as 1Ghz. |
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Regarding the cheaper-ness of accepting a high defect rate, I'm sure you are talking about the Law of Diminishing Returns. However, I'm not really talking about retrofitting some old Fab with brand-new air-scrubbing equipment; I'm talking about installing old equipment in a portion of a nice new already-existing Fab. Then that old equipment can make wafers with (continuing the examples in the main Idea) 4-micron lines, and reap the advantage of the cleanliness at that fab, with the result being near-zero-defect whole wafers. |
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Next, I do see your point about using thick in-wafer wiring between neighboring mounted chips. Still, if more power is needed, it should be possible to accommodate it. The wafer as a whole, of course, has contact points for communication with the outside world, and this includes power for its mounted chips. Perhaps those connecting lines can be AMPLIFIED connecting lines, although I realize this means adding largish transistors to the wafer (to beat the defects problem) -- and that in turn means they may not be able to keep up with the desired overall clock rate, for the mounted chips. I suppose it depends on how fancy those largish transistors are (gallium arsenide, maybe?). |
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I might add that the 4-micron connecting-wire-width was just a suggestion; perhaps something smaller can be used on the wafer, with zero show-stopping defects. Certainly the manufacturing steps for such wafer-wide-wiring will be somewhat fewer than for normal integrated-circuit manufacturing. |
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humanbean, thanks. But, did you not notice that one partial solution for the heat dissipation problem was right before your eyes in the middle of the Idea? Currently heat sinks are only attached to one side of a chip, because the other side has the connectors to the outside world. But here, if a chip is turned upside down and bonded to a wafer, then BOTH outer sides (of chip and wafer) can be glued to heat sinks! Only the circular edge of one side of the ordinary wafer (or rectangular edge of a large squarish wafer) would be unbonded, because that's where its connectors would be, to the outside world. |
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Regarding the Resistance/Capacitance thing, I do recognize the issue. Still, you do imply that appropriate simulations will allow them to be solved, and I would just consider this to be part of the overall up-front expenses associated with chip design. That is, if you are deliberately designing a CPU in pieces, then part of the design process includes investigating the connections between the pieces. |
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Not to mention that those connections don't necessarily ALL have to be from-chip-to-wafer-across-to-next-chip. Depending on how cleanly chips can be cut from a wafer, it seems to me that a chip could be provided with some EDGE-connection points, such that those points would be exposed when the chip is cut from the array in which it was manufactured. Then when mounted on a wafer, some of the connections would be through the wafer (power for example), and some would be directly edge-to-edge to the next chip on the wafer (communications). |
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1) Many complex chips (like CPUs) are designed with redundant components so that the failure of a particular part of the circuit (like cache memory) doesn't ruin the whole device.
2) I'm not sure you could solder - with any real precision - the various components of a CPU onto a PCB the size of a modern CPU. Furthermore, you're introducing multitudinous points of failure, should any given connection fail. |
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phoenix, the modern Ball Grid Array is an existing and working way to solder a whole lotta contacts at once, with apparently excellent reliability. I'm not suggesting much more than using smaller solder-balls -- and the precision alignment thing is a well-solved problem in the chip-making industry. |
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Yes, but now your connection points are huge and there are so many of them! Not only is it going to be inefficient (which you acknowledge) but I imagine the RF (both generated and received) will be tremendous. |
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And you're recouping what? What are the dollars lost figures here? 25% of a silicon wafer might amount to a couple hundred bucks - easily made up by the remaining silicon. Whatever the crossover, it's obviously something the fabricators are willing to put up with. |
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phoenix, on what basis do you assume that the connection points must be huge? They only need to be about the same size as the wiring inside the main wafer. Is that really much larger than the connection points that are already given to existing chips? As for being many of them, well, yes, there will be more than normal, since a multi-chip component needs interconnections as well as connections to the wafer. However, doesn't current chip design basically place all the contacts at the edges of a chip? Well, consider this:
...................
.___.___.___.
...................
.___.___.___.
...................
.___.___.___.
...................
Now I cannot draw as many vertical dots as horizontal, but if you imagine that, then you will see nine regions surrounded by connection points. That would be nine chips, of course, after the ORDINARY fashion. Are there no circuit boards out there with nine chips spaced so closely together? Well, all we are doing is removing their plastic packages and placing the chips even closer together! SO WHAT if I have specified that these chips might be subcomponents of some major overall thing like a CPU? If you want to instead install whole currently-existing CPU chips, be my guest! The goal is merely to cover the wafer with working and reliable circuits AS IF they had been been directly constructed into the wafer. |
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About the redundancy: yes, I am aware of it, but obviously it is not good enough, since they still have a significant yield of defective chips per wafer. That is the other reason why I'd like to see such assemblages as described here: the bad chips can be weeded out before being installed. |
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I mean that packaged as individual IC's, the components of a CPU will take up (I'm guessing) 10x more space and many if most runs (data paths) will be double (again guessing) in length. Again, they will be more susceptible to accepting and causing RFI. I also don't think that these surface mount components will be as easy to replace as you seem to think. |
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If you're not doing anything else to the manufacturing process to make manufacturing itself more reliable, what difference does it make what form factor you deliver your ICs in? I expect you'll end up with a 25% failure rate on each component (on average) because the process creating them hasn't changed. |
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Again I'll assert that whatever the failure rate is, it must be acceptable. Intel, AMD and Motorola aren't laying off, so far as I know. |
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phoenix, you are again not paying attention to what I wrote. I did not say that ANY chips would be "packaged as individual ICs". I am talking BARE chips here, mounted directly onto a wafer. This means that the interconnection distance between those chips is going to be far less than you have previously been thinking -- especially if direct edge-to-edge connections are employed. So, consider an existing CPU in which, for example, the Cache Memory is located next to the Instruction Decoder. They currently have connecting traces between them, right? In this scheme the two components could be two separate chips, but located/mounted edge-to-edge on a wafer. The connecting traces are the SAME, except slightly longer. The advantage, as stated previously, is that whole wafers of Instruction Decoders can be made, and whole wafers of Cache Memory can be made, only only good components would be placed together here. It remains true that the percentages of good chips is higher when they are smaller. So, if 100 major defects per wafer occur, and there are 200 large CPUs per wafer, then you likely have only 50% yield of good CPUs (unless lucky that some CPUs had multiple major defects). For six wafers, that would be 600 or so good CPUs. Now consider this alternative: **IF** each CPU has 6 same-sized components, and each component could be made at 1200 per wafer, then 100 major defects on the wafer still means 1100 good components from EACH of the six wafers. Thus 1100 good CPUs could be assembled from the components on six wafers, and not merely 600. I am not at all saying that the current manufacturing techniqes don't produce adequate numbers of good CPUs; I am merely saying that this is a way to get a lot MORE of them from the same number of wafers! Again, I agree that the slightly longer connections between components will have some effects, such as the greater RFI problem you mention, and slower operation speed, but I also think that these will not nearly be so bad as you have been thinking. And, of course, there is nothing to prevent continued current manufacturing of single-chip large CPUs -- for those who want to pay the price. |
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Next, I also did not say anything about replacing components. While I do understand that some chips work for a while and then go bad, others are bad even before they are cut from a wafer. THOSE are the ones that prevented the original version of Wafer Scale Integration, and which would be weeded out before being installed in this version of WSI. Since as you know not much is done these days for the chips that "work for a while and then go bad" (except replace whole circuit board), I would tend to think that the trend would be maintained. Sure, it would be nice if a good way was found to reliably mount any chip for easy removal. PERHAPS the overall mounting wafer can be manufactured with slight ridges that would allow emplaced chips (with beveled edges) to be nestled. In this scenario those ridges would have to contain conductive interconnection traces, but now we could use clamps on the heat sinks (one on the back of the wafer, and one on the back of all the mounted chips) to squish the works together, and maybe no soldering at all would be needed. Then replacing bad chips could be easy. |
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humanbean, it has been my understanding that the "flip chip" packaging still only allows a heat sink to be placed on only one side of a chip. Sure, it is the back side, and more surface area is available there than on the front side (where connection points have to be exposed), but it is still only one side. This scheme allows fairly intimate contact between each chip and the overall mounting wafer, so a good amount of heat from the chip should get into the wafer, and thence to the wafer's heat sink. Certainly this is better than having only one heat sink on only one side of a chip. (I could mention cooling fans too, but then we are exceeding the main scope of this Idea.) |
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I would say a lot can be learned from software engineering. OOP has demonstrated that modularity, and the flexibility it gives, is far superior, for any given system, than a continual drive for a smaller, hyper-integrated "system". Granted, this does require more overhead, in this case heat/speed/coupling issues. But these issues are ones that manufacturers are more easily to deal with, mainly becuase of cost. |
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